Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.
Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
Synthesis Tools: Synopsys DC/DCG/FC.
Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.
Scripting: TCL, Perl, or Python.
This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies
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Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.
Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
Synthesis Tools: Synopsys DC/DCG/FC.
Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.
Scripting: TCL, Perl, or Python.
Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.