ASIC Design Verification Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical/Computer Science Engineering, or equivalent practical experience.
- Experience verifying digital systems with standard IP components/interconnects, including microprocessor cores and hierarchical memory subsystems.
- Experience in verifying digital logic at RTL using SystemVerilog for FPGAs and ASICs.
- Experience verifying digital IP and subsystems.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Science, or a related field.
- Experience creating/using verification components and environments in methodology.
- Experience with image processing, computer vision, and/or machine learning applications.
- Experience in prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
- Experience with performance verification of ASIC components.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of IPs and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Identify verification holes and show progress towards tape-out.
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